Based on Intel® Core™ microarchitecture (code named Skylake) and manufactured on 14-nanometer process technology, these processors provide significant performance over the previous-generation Intel® Xeon® processor v4 product family. This Intel® Xeon® processor family introduces many new technologies and new instructions that will benefit integer operations and enhance security as well as a new feature to allocate the memory bandwidth.
A more in-depth discussion of the key features and architecture of the Intel® Xeon® processor Scalable family can be found in the technical overview document.
Key supported features
Intel® Memory Protection Extensions (Intel® MPX)
Intel® Memory Protection Extensions (Intel® MPX) checks for buffer overflows in software applications and checks to ensure that memory references intended at compile time do not become unsafe at runtime. Details on how to implement this feature under Windows® 10 can be found How to Protect Apps from Buffer Overflow Attacks. For developers working in Linux* environments, the article Intel® Memory Protection Extensions (Intel® MPX) to Linux*" will guide you through using Intel MPX.
More information about Intel MPX can be found in this enabling guide.
Intel® QuickAssist Technology (Intel® QAT)
Intel® QuickAssist Technology (Intel® QAT) helps accelerate compression and cryptographic tasks by offloading the data to hardware capable of optimizing those functions. Intel QuickAssist Technology can be used for:
- Bulk cryptography: Symmetric encryption and authentication, and cipher operations.
- Public key cryptography: Asymmetric encryption, digital signatures, and key exchange.
- Compression: Lossless data compression for data in flight and at rest.
An introduction to how Intel QuickAssist Technology benefits network functions can be found here. More about how this technology helps improve compression tasks is discussed in this collateral,which talks about Intel QuickAssist Technology and its compression services and shows what Intel QuickAssist Technology APIs to use and its execution flow. These videos show performance improvement using Intel QuickAssist Technology and explain how to find performance issue and troubleshoot installation problem.
Intel® Advanced Vector Extensions 512 (Intel® AVX-512 )
Intel® Advanced Vector Extensions 512 (Intel® AVX-512 ) is a new SIMD instruction set operating on 512-bit registers. It is a set of new instructions that can accelerate performance for applications in areas such as scientific simulations, financial analytics, and artificial intelligence. Intel AVX-512 is able to do that since it can pack 8 double-precision and 16 single-precision floating numbers within the 512-bit vectors, as well as 8 64-bit and 16 32-bit integers. To understand where to apply these instructions, read the article that discusses the use of Intel AVX-512 instructions in implementing the math functions. In order to use Intel AVX-512 in a high-level language such as C/C++, read this document that lists all intrinsic functions for Intel AVX-512.
The following example shows how to use intrinsic functions to process arrays of bits.
More detail about Intel AVX-512 can be found in Intel® Architecture Instruction Set Extensions Programming Reference.
Intel® Omni-Path Architecture (Intel® OPA)
Intel® Omnii-Path Architecture (Intel® OPA) offers low latency, low power consumption, and high throughput. A good overview of Intel OPA can be found in this document. Customers who want to implement Intel OPA will find this quick start guide useful. This guide outlines the basic steps for getting the Intel OPA cluster up and running. For more detail in installing software for Intel OPA, customers can refer to the Intel® Omni-Path Fabric (Intel® OP Fabric) Software installation guide, which shows how to install Intel OPA software and configure the Intel OPA chassis, switches, and so on. After the software has been installed, the next step is to set up and administer the fabric, and then fine-tune it to run efficiently on the customer system.
Reliability Accessibility Serviceability (RAS)
The Intel Xeon processors v5 introduces two new RAS features called Advanced Error Detection and Correction (AEDC) and Local Machine Check exception (LMCE).
AEDC improves fault detection within the Core Execution Engine using residue checking and parity protection techniques. AEDC tries to correct the fault by retrying the instructions. If the retry fails a fatal MCERR is triggered.
LMCE improves the Machine Check Architecture (MCA) recovery-execution path event and increases the possibility of recovery. It increases the possibility of recovery by letting the thread consuming uncorrected data handle the error without broadcasting the fatal MCERR events to the rest of threads in the system that will prevent system recovery.
More information can be found in the Intel Xeon processor scalable family new reliability features article.
Note: LMCE is an advanced RAS feature that only exists in four-socket systems or above.